In the field of integrated circuits, particularly those containing relatively large memory arrays such as dynamic random access memories (DRAMs), static random access memories (SRAMs), various types of read-only memories, as well as microprocessors and other logic circuits containing memories, the use of redundant elements to replace defective memory cells has become widespread. In such circuits, redundant rows, redundant columns, or both, are provided that can be programmed, by way of fuses or antifuses, to be selected by the row or column address value corresponding to the defective element. Data is thus stored in and retrieved from the redundant element in lieu of the defective element when the programmed address is presented. As a result, the manufacturing yield of the integrated circuit can be significantly improved, particularly for large memory array devices having small feature sizes, where even a single extremely small defect would otherwise cause the entire memory to be non-saleable.
As is well known in the field, upon power-up of an integrated circuit, the voltages and logic states internal to the circuit can initially enter into an indeterminate state, especially considering the uncontrolled manner in which circuits may be powered up. Certain of these states are highly undesirable, and indeed can cause internal damage to the circuit. For example, in conventional SRAMs having word lines for connecting the memory cells in a selected row to one or a pair of bit lines, the possibility exists where multiple word lines can power-up in an on state. As a result, memory cells in different rows which are powered-up in complementary states can be connected to one another via the same bit line, resulting in excessive DC current being dissipated.
By way of further background, application Ser. No. 588,609, filed Sep. 26, 1990, now U.S. Pat. No. 5,121,358, assigned to SGS-Thomson Microelectronics, Inc. and incorporated herein by this reference, describes a memory which ensures that multiple word lines do not power-up into an energized state. In this memory, latched repeaters are included between sub-arrays in the memory, for allowing only the selected row in the selected sub-array to be energized, thus saving power in normal operation. The undesirable power-up state is avoided in this memory by the coupling of a power-on reset signal to each of the latched repeaters which forces all row line portions to a de-energized state on power-up, thus preventing against excessive DC power dissipation due to multiple memory cells being selected for a given bit line pair.
In the case of a memory having redundant rows, however, where more than one primary row to be replaced is disconnected from the row decoder by the opening of a fuse, it is possible that the memory may power-up with multiple disabled word lines in an on-state, even if the power-on reset pulse is used to control the row decoder or repeater. Especially considering that the replaced rows may contain defective memory cells that are shorted to a power supply voltage or to ground, the possibility of excessive power dissipation exists in such memories.
Referring now to FIG. 1, a portion of a row decoder constructed and controlled according to the prior art will now be described in detail. This conventional decoder receives predecoded input signals PDA (one-of-eight), PDB (one-of-four) and PDC (one-of-eight) for selecting one of 256 word lines WL.sub.0 through WL.sub.255 according thereto. Word lines WL.sub.0 through WL.sub.255 are grouped in pairs, and are driven by shared NAND gates 40.sub.0 through 40.sub.127 which receive the predecoded input signals PDA, PDB, PDC.
The construction of shared NAND gate 40.sub.0 is illustrated in further detail in FIG. 1. Predecoded signal PDA.sub.0 is received at the gates of p-channel transistor 48a and n-channel transistor 49a which have their source/drain paths connected in series; the output of shared NAND gate 40.sub.0 that is for driving word line WL.sub.0 is coupled to the common drain node of transistors 48a, 49a. P-channel transistors 54a, 55a have their source/drain paths connected in parallel with transistor 48a, and have their gates connected to receive predecoded signals PDC.sub.0, PDB.sub.0, respectively. N-channel transistors 50, 52 have their source/drain paths connected in series with that of transistor 49a, between the common drain node and ground. Transistors 50, 52 are also shared by the portion of shared NAND gate 40.sub.0 which drives word line WL.sub.1, this other portion also including p-channel transistor 48b and n-channel transistor 49b connected in series similarly as transistors 48a, 49a, but which receive predecoded input signal PDA.sub. 1 ; parallel p-channel transistors 54b, 55b have their source/drain paths connected in parallel with that of transistor 48b, with their gates also controlled by predecoded signals PDC.sub.0, PDB.sub.0, respectively. Accordingly, a word line WL can be energized by the NAND of its associated predecoded signals PDA, PDB, PDC; for example, word line WL.sub.1 can be driven by the NAND of predecoded signals PDA.sub.1, PDB.sub.0, PDC.sub.0.
For each word line WL, fuse 42 is connected in series with each of the outputs of shared NAND gate 40, through which, when intact, the word line signal is driven, and by which, when open, the word line signal is disabled. Fuses 42 are conventional fuses used in the implementation of redundant elements in memory circuits, for example polysilicon fuses openable by energy from a laser beam. For example, fuse 42.sub.0 is connected to the common drain node of transistors 48a, 49a. The opposite side of each fuse 42 is coupled, via an inverter 45, to its associated word line WL. Small p-channel latching transistor 46 has its source/drain path connected between V.sub.cc and the input of its associated inverter 45, and has its gate coupled to the output of its associated inverter 45, and thus will serve to maintain the de-energized state of its associated word line WL unless the shared NAND gate 40 associated therewith overpowers the drive of transistor 46. As a result, the opening of fuse 42 for a word line WL disables the shared NAND gate 40 from controlling the state of its associated word line WL.
It is necessary that the word line WL remain in a de-energized state for any row which is disabled by the opening of its fuse 42. Accordingly, a p-channel transistor 44 is connected in parallel with each of the latching transistors 46, and which has its gate driven by line CEc; line CEc corresponds to a chip enable signal, which in this example is generated by the logical NAND of the state of two chip enable terminals (CE1, CE2) at the output of NAND function 41. Accordingly, when the memory is enabled by chip enable terminal CE1 high and chip enable terminal CE2 low, such that line CEc is low and transistors 44 are turned on, the state of each word line WL, including those having their fuses 42 blown, is set to the de-energized state. Transistors 44 (similarly as transistors 46) are preferably sufficiently small that shared NAND gates 40 can overpower their drive and pull the input of inverter 45 low for the one of word lines WL that is to be energized.
Specifications for modern low power memories, particularly SRAMs, require that there be no DC current path during standby, including those times during which the memory chip is not enabled. This is accomplished by the turning off of all transistors 44 responsive to a deselect state at the chip enable terminals CE1, CE2, causing line CEc to be high. In such a standby condition, the row address value for one row will be indicated as a low logic level at the output of its shared NAND gate 40, but no DC current will be drawn through an on transistor 44 and the n-channel transistors 49, 50, 52 in the selected shared NAND gate 40; for the selected word line WL, its latching transistor 46 will be off since its word line WL is energized. For all unselected word lines WL, p-channel transistors 46 will remain on, maintaining the de-energized state.
It has been observed, however, that the input to inverter 45 in the decoder of FIG. 1 can be placed in an indeterminate state on power-up for those rows which have their fuses 42 opened, such that disabled rows may have their word line WL energized on power-up. Once this occurs, during standby (i.e., line CEc high) or during the initial portion of the first access after standby (transistors 44 being relatively small), multiple word line selection can result, causing high current drain, access time push-out in the initial access, or other erroneous operation including circuit failure. It is therefore an object of the present invention to provide a memory having power-on reset control of word lines which are disconnected from the row decoder due to their being replaced by a redundant row.
It is a further object of the present invention to provide such a memory where the word lines include latches for maintaining a de-energized state on disabled word lines during normal operation.
It is a further object of the present invention to provide such a memory in which no DC current is drawn in the row selection circuitry during standby.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.